Cadence and NVIDIA Claim 40x Faster RTL Verification With AI Agents

Cadence and NVIDIA say their design verification agent compresses RTL verification cycles from weeks to hours — more than 40 times faster — by automating the loop of simulation, formal verification, debugging, and code repair. The claim is about verification cycles, not the entire chip design process end to end.

The bottleneck sits inside a larger engineering problem. Hundreds of thousands of NVIDIA chips come together into the AI factories used to power frontier AI models. Designing those chips and the systems they run in means working with trillions of transistors, three-dimensional circuits, microscopic features, and timing relationships synchronized to picoseconds. The requirement is framed starkly: every gate and wire must work in harmony, with “no margin for error.”

Physical prototypes are too slow and too costly for that iteration, so the work happens in the digital design environment. Each chip begins as architectural specifications, which are translated into RTLA hardware design representation used before chip implementation., described as “the language of chip design.” A diagram maps Rubin GPU, Vera CPU, BlueField-4 DPU, and NVLink-6 into blocks of RTL code and then into digital waveforms.

The cost of failure at this stage is stated plainly: RTL must be verified in simulation, and “a single bug can delay a chip by months.” A displayed code editor highlights an RTL assignment related to a branch-unit address mismatch:

assign o_branch_unit_addr_mismatch = istaken && (i_branch_unit_targetPC[0]);

The point is not that this one line explains the whole verification problem. It shows the level at which the work becomes concrete: specific hardware logic, represented in code, must be exercised and checked before the design moves toward physical implementation.

At NVIDIA scale, verification is described as a large recurring workload: thousands of engineers, billions of compute hours per year, and millions of tests that are written, run, and debugged. That cycle takes teams weeks.

Cadence and NVIDIA’s answer is an orchestrated agent system. Codex coordinates the process. Cadence ChipStack launches the RTL verification loop. Nemotron powers the system. NVIDIA OpenShell secures it. The system calls on expert sub-agents for RTL generation, testbench creation, regression testing, and debug.

A terminal view captures the handoff from human instruction to agent workflow. The user asks the agent to “verify and fix this design with chipstack.” The response says it is using the “formal-agent skill” because the request is to verify and fix the design with ChipStack. A human prompt starts the work, but the task is routed into a structured verification capability rather than treated as a one-step command.

In the Cadence-attributed architecture diagram, the system is labeled “ChipStack Super Agent.” RTL and specs feed in. Coverage metrics, bug reports, logfiles, and RTL come out. A Codex Agent connects to the ChipStack Super Agent, which sits with a Mental Model Agent, Unit Test Agent, Formal Agent, and RTL Agent. OpenShell appears as the base layer under the stack.

The strongest technical claim is that the system drives a verification loop rather than merely running a test suite. ChipStack agents run hundreds of simulations with Cadence Xcelium and formal verification with Jasper. Design flaws are revealed. Bugs in the code are fixed.

The architecture separates, but connects, dynamic simulation and formal methods. The Unit Test Agent branches into parallel tasks using Xcelium. The Formal Agent generates tasks using Jasper. Cadence and NVIDIA present both as parts of the same agent-driven process.

That matters because the verification cycle contains several different kinds of work: generating or maintaining RTL, creating testbenches, running regressions, inspecting failures, debugging, and rerunning checks after changes. The agent system is positioned as a way to compress that loop by assigning those tasks to specialized agents operating within ChipStack.

A ChipStack interface displays a “Simulation Test Plan Scenarios” tab alongside generated code. One scenario is labeled “PushFiveAndShrinkCreditRecovery,” with steps including “Generate code” and “Run test,” and a final result of “Passed.” The screen illustrates the workflow shape being claimed: a verification scenario moves through generated code, execution, and recorded result.

Cadence and NVIDIA describe the system as driving itself through simulations, formal verification, bug discovery, and code fixes. The source description adds the operating boundary: major design issues are escalated for human review. Routine verification-loop work is automated; larger design problems still have a path back to engineers.

That boundary is important because the work is both repetitive and high consequence. Verification involves millions of tests and billions of compute hours, but the design has no margin for error, and a single bug can delay a chip by months. ChipStack is framed as a compression layer around that work: it can run simulations, invoke formal tools, debug failures, repair code, and report results, without presenting major design decisions as fully delegated to agents.

The broader claim connects chip verification back to AI infrastructure. The chips being verified are components of the AI factories used for frontier AI workloads, and the closing data-center image is labeled CoreWeave. Cadence and NVIDIA position AI agents as tools for accelerating the design of the hardware systems that support large-scale AI computation.